The present invention relates generally to a bipolar transistor and a method of manufacturing the bipolar transistor, and more particularly to a heterojunction bipolar transistor (HBT) in which parasitic emitter resistance is effectively reduced.
Conventionally, in order to reduce emitter resistance of a heterojunction bipolar transistor, there is known a method in which a composition graded layer, i.e., a layer in which the composition is graded, sloped or inclined is inserted between an emitter cap layer and an emitter layer, and thereby an increase in the emitter resistance caused by the discontinuity of a conduction band is suppressed. Such method is described, for example, in a thesis xe2x80x9cHigh Performance InGaP/GaAs HBTs with AlGaAs/InGaP Emitter Passivated Ledges for Reliable Power Applicationsxe2x80x9d, TuP24, Digest Book of International Electron Device Meeting 1997, page 361.
An explanation will be made in detail on a structure of a conventional HBT which uses an InGaP layer as an emitter layer and which adopts the above-mentioned method to reduce emitter resistance.
FIG. 9 is a sectional view illustrating an example of a epitaxial layer structure of a conventional HBT which uses an InGaP emitter layer. In the structure of FIG. 9, n type GaAs subcollector layer 2, n type GaAs collector layer 3, and p type InGaAs composition graded base layer 4 are sequentially formed or laminated on a semi-insulating GaAs substrate 1 which is hereafter referred to also as a semi-insulating substrate. The n type GaAs subcollector layer 2 is hereafter referred to also as an n type collector contact layer, and the n type GaAs collector layer 3 is hereafter referred to also as an n type collector layer. The p type InGaAs composition graded layer 4 is referred to also as a xe2x80x9cbase layer 4xe2x80x9d or a xe2x80x9clayer 4xe2x80x9d hereafter. On a part of the n type GaAs subcollector layer 2 and on a part of the base layer 4, a collector electrode 10 and a base electrode 11 are respectively formed by vapor deposition. On the base layer 4, an n type InGaP emitter layer 5 is formed. Hereafter, the n type InGaP emitter layer 5 is also referred to as an n type emitter layer 5, an emitter layer 5 or a layer 5. On the emitter layer 5, an n type AlGaAs composition graded layer 6, in which Al composition is graded, is formed. Hereafter, the n type AlGaAs composition graded layer 6 is referred to also as a layer 6. The impurity concentration of each of the layer 5 and the layer 6 is set to a low value to avoid increase in the base-emitter capacity, and is set to a value between 1xc3x971017 cmxe2x88x923 and 5xc3x971017 cmxe2x88x923. The layer 6 is provided to avoid occurrence of discontinuity of the conduction band between the n type InGaP emitter layer 5 and an n type GaAs cap layer 8, stacked on the layer 6, and thereby to suppress increase in the emitter resistance. Hereafter, the n type GaAs cap layer 8 is also referred to as the xe2x80x9clayer 8xe2x80x9d. An n type composition graded InGaAs contact layer 9 which is stacked on the layer 8 and which is hereafter referred to also as xe2x80x9clayer 9xe2x80x9d is used to decrease contact resistance between an emitter electrode 12 stacked on the layer 9 and the layer 8. Both the layer 8 and the layer 9 are set to have a high impurity concentration equal to or larger than 1xc3x971018 cmxe2x88x923 to decrease resistance thereof. FIG. 10 shows a distribution of impurity concentration and a distribution of Al composition from the layer 5 to the layer 9 in the conventional heterojunction bipolar transistor shown in FIG. 9.
A hetero guard ring portion 13 is provided to protect the surface of the base layer 4 between the base electrode 11 and the emitter electrode 12. By providing the hetero guard ring 13, it becomes possible to greatly decrease the surface recombination current at the surface of the base layer 4. The hetero guard ring portion 13 can be formed, after etching the layer 9, by selectively etching the layer 8 by means of selective dry etching of AlGaAs/GaAs and by leaving the layer 6. It is necessary that the hetero guard ring portion 13 is completely depleted. Therefore, when, for example, the total thickness of the layer 5 and the layer 6 is 60 nm, it is necessary that the impurity concentration of layer 6 as well as the layer 5 is set to at most a value equal to or lower than 5xc3x971017 cmxe2x88x923.
Now, explanation will be made as to the reasons why the emitter resistance, i.e., the resistance from the interface between the layer 5 and the base layer 4 to the emitter electrode 12, is high in the above-mentioned prior art HBT structure.
In the HBT structure shown in FIG. 9, a composition graded layer is used and, therefore, potential barrier caused by the discontinuity of conduction band does not occur. However, the emitter resistance becomes large by the reasons mentioned below.
In FIG. 11, a solid line shows a characteristic of a differential resistivity of an emitter from the layer 5 to the layer 9 in the conventional HBT. The ordinate designates differential resistivity in ohm/micrometer, and the abscissa designates distance or position between the layer 5 and the layer 9 in micrometer. The area of the emitter is 10 square micrometers. The differential resistivity r(x) is represented by the expression (1) below. In the graph of FIG. 11, the area of a portion surrounded by the curve the differential resistivity r(x) and the abscissa becomes equal to the emitter resistance Re.
Re=∫r(x)dxxe2x80x83xe2x80x83(1)
In FIG. 11, the dotted line shows a characteristic of a differential resistivity of a bulk calculated from the sheet resistances of the layer 5 and the layer 6. In the graph of FIG. 11, when the area surrounded by the solid line and the abscissa, that is, the emitter resistance, is compared with the area surrounded by the dotted line and the abscissa, that is, the bulk resistance, it can be seen that the emitter resistance becomes higher than the bulk resistance in the vicinity of the n type AlGaAs composition graded layer 6.
The reason why the differential resistivity becomes higher from the layer 6 toward the layer 5 is as follows. Since, in the layer 6, electron affinity varies with the gradient of composition, charge transfer occurs in the layer 6 and electron concentration reduces locally in the vicinity of the interface between the layer 6 and the layer 5.
FIG. 12 shows a distribution of electron concentration from the layer 5 to the layer 9 of the conventional HBT. From FIG. 12, it can be seen that electron concentration becomes high on the side of the layer 8 in the layer 6, and on the other hand electron concentration reduces in the vicinity of the interface between the layer 6 and the layer 5.
In the conventional structure shown in FIG. 9, there is a disadvantage in that the emitter resistance, that is, a resistance from the interface between the layer 5 and the base layer 4 to the emitter electrode 12, is considerably higher than the sum of bulk resistance calculated from the sheet resistance from the layer 5 to the layer 9 constituting an emitter and contact resistance between the electrode 12 and the layer 9. This is because, in the n type AlGaAs composition graded layer 6, electron affinity decreases according to the increase in Al composition toward the n type InGaP emitter layer 5. Due to such decrease in electron affinity, electron concentration within the layer 6 greatly decreases toward the n type InGaP emitter layer 5, and, due to the decrease in the electron concentration, a high resistance portion is produced in the vicinity of the interface between the layer 6 and the layer 5.
It is a main object of the present invention to provide a heterojunction bipolar transistor whose emitter resistance is made lower than that of a conventional heterojunction bipolar transistor.
It is another object of the present invention to provide an epitaxial structure for a heterojunction bipolar transistor in which a hetero guard ring for protecting surface of a base layer between an emitter electrode and a base electrode can be easily formed.
According to an aspect of the present invention, there is provided a bipolar transistor comprising: a semi-insulating substrate; a collector contact layer formed on the semi insulating substrate and having a first conductivity type; a collector layer formed on the collector contact layer and having the first conductivity type; a base layer formed on the collector layer and having a second conductivity type which is different from the first conductivity type; and an emitter layer formed on the base layer and having the first conductivity type. A forbidden band width of the emitter layer is wider than that of the base layer. The bipolar transistor further comprises: a composition graded layer formed on the emitter layer and formed of a semiconductor material having the first conductivity type; and an emitter contact layer formed on the composition graded layer and having the first conductivity type. A forbidden band width of said emitter contact layer is narrower than that of the emitter layer and impurity concentration of the emitter contact layer is higher than that of the emitter layer. Composition of the composition graded layer is inclined so as to avoid discontinuity of conduction band or valence band at the interface between the composition graded layer and the emitter layer and at the interface between the composition graded layer and the emitter contact layer, and impurity concentration of the composition graded layer is higher than that of the emitter layer.
According to another aspect of the present invention, there is provided a method of manufacturing a bipolar transistor comprising: providing a semi-insulating substrate; forming a collector contact layer having a first conductivity type on the semi-insulating substrate; forming a collector layer having the first conductivity type on the collector contact layer; forming a base layer having a second conductivity type which is different from the first conductivity type on the collector layer; and forming an emitter layer having the first conductivity type on the base layer. A forbidden band width of the emitter layer is wider than that of the base layer. The method further comprises: forming a composition graded layer made of a semiconductor material which is different from that forming the emitter layer and which has the same conductivity type as the conductivity type of the emitter layer, on the emitter layer; and forming an emitter contact layer having the first conductivity type on the composition graded layer. A forbidden band width of the emitter contact layer is narrower than that of the emitter layer and impurity concentration of the emitter contact layer is higher than that of the emitter layer. The method still further comprises: removing part of the emitter contact layer by etching, and thereby exposing part of the composition graded layer; and etching the exposed part of the composition graded layer to expose part of the emitter layer, by using an etching method in which etching rate of the composition graded layer is higher than that of the emitter layer. Composition of the composition graded layer is inclined so as to avoid discontinuity of conduction band or valence band at the interface between the composition graded layer and the emitter layer and at the interface between the composition graded layer and the emitter contact layer; and impurity concentration of the composition graded layer is higher than that of the emitter layer.
In the heterojunction bipolar transistor according to the present invention, the composition graded layer itself is made to have a high concentration, and thereby it becomes possible to suppress reduction of electron concentration caused by the gradient of electron affinity due to the composition gradient, and to suppress formation of a high resistance portion.